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(R)
DG401, DG403
Data Sheet November 20, 2006 FN3284.11
Monolithic CMOS Analog Switches
The DG401 and DG403 monolithic CMOS analog switches have TTL and CMOS compatible digital inputs. These switches feature low analog ON resistance (<45) and fast switch time (tON<150ns). Low charge injection simplifies sample and hold applications. The improvements in the DG401, DG403 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 30VP-P signals. Power supplies may be single-ended from +5V to +34V, or split from 5V to 17V. The analog switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a 15V analog input range. The three different devices provide the equivalent of two SPST (DG401) or two SPDT (DG403) relay switch contacts with CMOS or TTL level activation. The pinout is similar, permitting a standard layout to be used, choosing the switch function as needed.
Features
* ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 45 * Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . .<35W * Fast Switching Action - tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns - tOFF (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns * Low Charge Injection * DG401 Dual SPST; Same Pinout as HI-5041 * DG403 Dual SPDT; DG190, IH5043, IH5151, HI-5051 * TTL, CMOS Compatible * Single or Split Supply Operation * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Audio Switching * Battery Operated Systems * Data Acquisition * Hi-Rel Systems * Sample and Hold Circuits
Pinouts
DG401 (16 LD SOIC, TSSOP) TOP VIEW
D1 1 NC 2 NC 3 NC 4 NC 5 NC 6 NC 7 D2 8 16 S1 15 IN1 14 V13 GND 12 VL 11 V+ 10 IN2 9 S2
* Communication Systems * Automatic Test Equipment
Ordering Information
PART NUMBER* DG401DY* DG401DYZ* (Note) DG401DVZ* (Note) DG403DY* DG403DYZ* (Note) DG403DVZ* (Note) PART TEMP. MARKING RANGE (C) DG401DY DG401DYZ DG401 DVZ DG403DY DG403DYZ DG403 DVZ -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE 16 Ld SOIC 16 Ld SOIC (Pb-free) PKG. DWG. # M16.15 M16.15
16 Ld TSSOP M16.173 (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) M16.15 M16.15
DG403 (16 LD SOIC, TSSOP) TOP VIEW
D1 1 NC 2 D3 3 S3 4 S4 5 D4 6 NC 7 D2 8 16 S1 15 IN1 14 V13 GND 12 VL 11 V+ 10 IN2 9 S2
16 Ld TSSOP M16.173 (Pb-free)
*Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
NOTE: (NC) No Connection.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 1999, 2002-2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
TRUTH TABLE DG401 LOGIC 0 1 NOTE: SWITCH OFF ON DG403 SWITCH 1, 2 OFF ON SWITCH 3, 4 ON OFF
Logic "0" 0.8V. Logic "1" 2.4V.
Functional Diagrams
DG401
VL 12 S1 16 V+ 11 1 D1 S1 S3 IN1 15 IN2 S2 10 16 VL 12
DG403
V+ 11 1 D1 D3
4
3
IN1 15 IN2 8 D2 S2 S4 13 GND VSWITCHES SHOWN FOR LOGIC "1" INPUT 14 10
9
9
8
D2 D4
5 13 GND 14 V-
6
Schematic Diagram
V+ SOURCE
VVL
VIN V+ GND V-
DRAIN
2
FN3284.11 November 20, 2006
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) +0.3V Digital Inputs VS , VD (Note 1) . . . . . (V-) -2V to (V+) + 2V or 30mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle, Max) . . 100mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature (Plastic Package). . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300C (SOIC and TSSOP- Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V (Max) Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max) Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min) Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Signals on SX , DX , or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V (Note 3), VL = 5V, Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 4) MIN (NOTE 5) TYP (NOTE 4) MAX UNITS
PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay (DG403), tD Charge Injection, Q (Figure 3) OFF Isolation (Figure 4) Crosstalk (Channel-to-Channel) (Figure 6) Source OFF Capacitance, CS(OFF) Drain OFF Capacitance, CD(OFF) Channel ON Capacitance, CD(ON) + CS(ON) DIGITAL INPUT CHARACTERISTICS Input Current with VIN Low, IIL Input Current with VIN High, IIH ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON)
RL = 300, CL = 35pF
+25 +25
5 -
100 60 12 60 72 -90 12 12 39
150 100 -
ns ns ns pC dB dB pF pF pF
RL = 300, CL = 35pF CL = 10nF, VG = 0V, RG = 0 RL = 100, CL = 5pF, f = 1MHz
+25 +25 +25 +25
f = 1MHz, VS = VD = 0V (Figure 7)
+25 +25 +25
VIN Under Test = 0.8V, All Others = 2.4V VIN Under Test = 2.4V, All Others = 0.8V
Full Full
-1 -1
0.005 0.005
1 1
A A
Full V+ = 13.5V, V- = -13.5V, IS = 10mA, VD = 10V +25 Full +25 Full +25 Full +25 Full
-15 -0.5 -5 -0.5 -5 -1 -10
20 3 -0.01 -0.01 -0.04 -
15 45 55 3 5 0.5 5 0.5 5 1 10
V nA nA nA nA nA nA
rDS(ON) Matching Between Channels, rDS(ON) V+ = 16.5V, V- = -16.5V, IS = -10mA, VD = 5, 0, -5V Source OFF Leakage Current, IS(OFF) V+ = 16.5V, V- = -16.5 VD = 15.5V, VS = 15.5V
Drain OFF Leakage Current, ID(OFF) V = 16.5V, VD = VS = 15.5V
Channel ON Leakage Current, ID(ON) + IS(ON)
+25 Full
3
FN3284.11 November 20, 2006
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V (Note 3), VL = 5V, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (C) (NOTE 4) MIN (NOTE 5) TYP (NOTE 4) MAX UNITS
PARAMETER POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+
V+ = 16.5V, V- = -16.5V, VIN = 0V or 5V
+25 Full +25 Full
-1 -5 -1 -5
0.01 -0.01 0.01 -0.01 -
1 5 1 5 -
A A A A A A A A
Negative Supply Current, I-
Logic Supply Current, IL
+25 Full
Ground Current, IGND
+25 Full
NOTES: 3. VIN = input voltage to perform proper function. 4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Test Circuits and Waveforms
3V LOGIC INPUT 50% 0V tOFF SWITCH INPUT SWITCH OUTPUT VS VO 0V tON SWITCH INPUT -VS (NOTE 7) 10% 0V -15V 90% 90% LOGIC INPUT GND VSWITCH INPUT S1 IN1 RL CL tr < 20ns tf < 20ns 5V VL +15V V+ RL = 300 CL = 35pF D1 VO
NOTES: 6. Logic input waveform is inverted for switches that have the opposite logic sense. 7. VS = 10V for tON , VS = -10V for tOFF. FIGURE 1A. MEASUREMENT POINTS
Repeat test for IN2 and S2. For load conditions, see Specifications. CL includes fixture and stray capacitance. RL V O = V S ----------------------------------R L + r DS ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
4
FN3284.11 November 20, 2006
Test Circuits and Waveforms
3V LOGIC INPUT 0V VS1 SWITCH OUTPUT (VO1) 90% 0V VS2 SWITCH OUTPUT (VO2)
(Continued)
5V VL VS1 = 10V VS2 = 10V IN1 LOGIC INPUT 90% GND 0V tD tD
+15V V+
RL = 300 CL = 35pF D1 D2 VO2 RL1 VO1 CL1
RL2 V-15V
CL2
0V
CL includes fixture and stray capacitance. FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. BREAK-BEFORE-MAKE TIME
5V VL SWITCH OUTPUT VO VO RG
+15V V+ D1 VO
INX
ON
OFF
ON
VG
CL GND V-
Q = VO x CL 0V -15V
FIGURE 3A. MEASUREMENT POINTS FIGURE 3. CHARGE INJECTION
FIGURE 3B. TEST CIRCUIT
C SIGNAL GENERATOR
V+
+15V
+5V
VL
C SIGNAL GENERATOR
C
V+
+15V
+5V
VL
C
VS
VS
INX
0V, 2.4V
INX
0V, 2.4V
ANALYZER RL
VD C
ANALYZER V-15V RL
VD C
GND
GND
V-15V
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. INSERTION LOSS TEST CIRCUIT
5
FN3284.11 November 20, 2006
Test Circuits and Waveforms
(Continued)
C SIGNAL GENERATOR
V+
+15V
+5V VL C +15V C V+ +5V VL C
VS1
VD1
50 VS
0V, 2.4V
IN1
IN2
0V, 2.4V IMPEDANCE ANALYZER NC C VD
INX
0V, 2.4V AS REQUIRED
ANALYZER RL
VD2
VS2
GND
V-15V GND
V-15V
C
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCES TEST CIRCUIT
Application Information
Dual Slope Integrators
The DG403 is well suited to configure a selectable slope integrator. One control signal selects the timing capacitor C1 or C2 . Another one selects eIN or discharges the capacitor in preparation for the next integration cycle.
Peak Detector
A3 acting as a comparator provides the logic drive for operating SW1 . The output of A2 is fed back to A3 and compared to the analog input eIN . If eIN > eOUT the output of A3 is high keeping SW1 closed. This allows C1 to charge up to the analog input voltage. When eIN goes below eOUT, A3 goes negative, turning SW1 off. The system will therefore store the most positive analog input experienced.
+5V VL eIN S1 S3
+15V V+ D1 D2 eOUT RESET
IN1 INTEGRATE/ RESET S2 S4 IN2 DG403 SCOPE SELECT GND V-15V D3 D4 C2 + A3 C1 + eIN A1
SW2
SW1
R1
A2 + -
TTL
eOUT
C1 DG401
FIGURE 8. DUAL SLOPE INTEGRATOR
FIGURE 9. POSITIVE PEAK DETECTOR
6
FN3284.11 November 20, 2006
Typical Performance Curves
10 V+ = 15V V- = -15V TA = 20C 4 VL = 5V TA = 25C 3
8
6 VT (V) VT (V) 18 20 DG403 SW3, 4 2
4
1 2
0 0 2 4 6 8 10 12 VL (V) 14 16
0 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 20
FIGURE 10. INPUT SWITCHING THRESHOLD vs LOGIC SUPPLY VOLTAGE
FIGURE 11. INPUT SWITCHING THRESHOLD vs POWER SUPPLY VOLTAGE
40 35 V+ = 15V V- = -15V VL = 5V
60 TA = 25C 50
30 rDS(ON) () rDS(ON) () 125C 25 85C 20 25C 0C 15 10 -15 -40C -55C 10 -10 -5 0 VD (V) 5 10 15 -25 -15 -5 VD (V) 5 15 25 40 V+ = 12V, V- = -12V V+ = 15V, V- = -15V V+ = 20V, V- = -20V V+ = 6V, V- = -6V V+ = 10V, V- = -10V V+ = 22V, V- = -22V
30
20
FIGURE 12. rDS(ON) vs VD AND TEMPERATURE
FIGURE 13. rDS(ON) vs VD AND POWER SUPPLY VOLTAGE
70 60 V+ = 7.5V 50 rDS(ON) ()
V- = 0V TA = 25C
200 180 160 140 Q (pC) V+ = 15V V- = -15V VL = 5V CL = 10nF
V+ = 10V 40 V+ = 12V 30 V+ = 15V V+ = 20V 20 10 0 5 10 VD (V) 15 20 25 V+ = 22V
120 100 80 60 40 20 0 -15 -10 -5 0 VS (V) 5 10 15 CL = 100pF CL = 1nF
FIGURE 14. rDS(ON) vs VD AND SINGLE SUPPLY VOLTAGE
FIGURE 15. CHARGE INJECTION vs SOURCE VOLTAGE
7
FN3284.11 November 20, 2006
Typical Performance Curves
0.0
(Continued)
100.0 10.0 RL = 600 1.0 IS(OFF) (nA) 0.1 0.01 0.001 0.0001 TYPICAL V+ = 15V V- = -15V VL = 5V VD = 14V
-0.5
LOSS (dB)
-1.0
RL = 75
-1.5 V+ = 15V, V- = -15V VL = 5V, VS = 1VRMS SEE INSERTION LOSS TEST SETUP (FIGURE 5) RL = 50
-2.0
10K
100K
1M FREQUENCY (Hz)
10M
-55 -35
-15
5
25
45
65
85
105
125
TEMPERATURE (C)
FIGURE 16. INSERTION LOSS vs FREQUENCY
FIGURE 17. IS(OFF) vs TEMPERATURE
100.0 10.0 1.0
V+ = 15V V- = -15V VL = 5V VD = 14V ID(ON) + IS(ON) (nA)
100.0 10.0 1.0
V+ = 15V V- = -15V VL = 5V VD = 14V
ID(OFF) (nA)
TYPICAL 0.1 0.01 0.001 0.0001 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
TYPICAL 0.1 0.01 0.001 0.0001 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
FIGURE 18. ID(OFF) vs TEMPERATURE
FIGURE 19. ID(ON) + IS(ON) vs TEMPERATURE
90 60 30 0 -30
10.0 WHEN VANALOG EXCEEDS POWER SUPPLY, SWITCH SUBSTRATE DIODES BEGIN TO CONDUCT I+, I -, IL , (A) V+ = 15V V- = -15V VL = 5V I0.1 I+
1.0
IL ID(OFF) , IS(OFF) ID(ON) + IS(ON)
IS , ID (pA)
0.01 IL
-60 -90 -120 -150 -20 -15 -10 -5 0 VS , VD (V) 5 10 15 20 V+ = 15V, V- = -15V VL = 5V, TA = 25C ID(OFF) , VS = 0V IS(OFF) , VD = 0V
0.001
I0.0001 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
FIGURE 20. LEAKAGE CURRENTS vs ANALOG VOLTAGE
FIGURE 21. SUPPLY CURRENT vs TEMPERATURE
8
FN3284.11 November 20, 2006
Typical Performance Curves
20 15 10 5 VS (V) 0 -5 -10 -20 SEE BBM TEST SETUP (FIGURE 2) -15 0 10 20 30
(Continued)
40 V+ = 15V V- = -15V VL = 5V tON , tOFF (ns) 35 30 VS = 10V 25 20 15 10 5 0 40 50 0 5 SEE BBM TEST SETUP (FIGURE 2) 10 15 20 25 VS = -10V VL = 5V
NOT MEASURABLE DUE TO CAPACITIVE FEEDTHROUGH
BREAK-BEFORE-MAKE TIME (ns)
SUPPLY VOLTAGE (V)
FIGURE 22. BREAK-BEFORE-MAKE vs ANALOG VOLTAGE
FIGURE 23. BREAK-BEFORE-MAKE vs POWER SUPPLY VOLTAGE
600 540 480 420 tON , tOFF (ns) 360 300 240 tON , VS = 10V 180 120 60 0 0 1 2 tOFF, VS = -10V 3 VIN (V) 4 5 6 tON , VS = -10V tOFF, VS = 10V tON , tOFF (ns) V+ = 15V V- = -15V VL = 5V
240 210 180 150 120 90 60 30 0
V+ = 15V V- = -15V VL = 5V tON , VS = 10V
tOFF , VS = -10V tON , VS = -10V tOFF, VS = 10V
-55 -35
-15
5
25
45
65
85
105 125
TEMPERATURE (C)
FIGURE 24. SWITCHING TIME vs INPUT LOGIC VOLTAGE (NOTE 8)
FIGURE 25. SWITCHING TIME vs TEMPERATURE (NOTE 8)
200 180 160 140 tON , tOFF (ns) 120 100 80 60 40 20 0 0
VS = 5V tON VS = -5V tON
300 VL = 5V 270 240 210 tON , tOFF (ns) 180 150 120 90 60 30 0 5 10 15 SUPPLY VOLTAGE (V) 20 25 0 5 10 15 20 25 POSITIVE SUPPLY (V) tOFF V- = -15V tON V- = -5V V- = 0V V- = 0V V- = 0V V- = -5V V+ = = -15 V- -15V tON tON VS = 5V
VS = 5V tOFF
VS = -5V tOFF
FIGURE 26. SWITCHING TIME vs POWER SUPPLY VOLTAGE (NOTE 8)
FIGURE 27. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE (NOTE 8)
9
FN3284.11 November 20, 2006
Typical Performance Curves
300 270 240 210 tON , tOFF (ns) 180 150 120
(Continued)
VS = -5V
V- = -5V tON V- = -15V V- = -15V tON tOFF tOFF 0 5 10 15 20 25
90 60 30 0 V- = -5V
POSITIVE SUPPLY (V)
FIGURE 28. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE (NOTE 8) NOTE: 8. Refer to Figure 1 for test conditions.
10
FN3284.11 November 20, 2006
Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 NOTES 9 3 4 6 7 8 Rev. 1 2/02
A1 0.10(0.004) A2 c
E1 e E L N
e
b 0.10(0.004) M C AM BS
0.026 BSC 0.246 0.020 16 0 8 0.256 0.028
0.65 BSC 6.25 0.50 16 0 6.50 0.70
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
11
FN3284.11 November 20, 2006
Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 16 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 16 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN3284.11 November 20, 2006

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